A Novel Conflict-Free Parallel Memory Access Scheme for FFT Processors

Abstract

This brief presents a novel conflict-free access scheme for memory-based fast Fourier transform (FFT) processors. It is proved to satisfy the constraints of the mixed-radix, continuous-flow, parallel-processing, and variable-size FFT computations. An address generation unit is also designed and outperforms existing architectures with reduced gate delay and lower hardware complexity.