2002 · 15 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsVlsi DesignCmos Circuit DesignDigital Integrated Circuit DesignDigital Logic DesignDynamic Power ReductionIntegrated Circuit DesignLow-power Digital Circuit DesignCmos Logic CircuitsCmos Logic DesignCurrent-mode LogicDynamic Logic CircuitsLogic Family DesignLow-power Cmos DesignLow-power Logic DesignNoise Immunity
This paper presents a new logic style DyCML for low-power high-performance VLSI applications. The new logic family combines the speed, low supply voltage and noise immunity advantages of MCML circuits while achieving the low standby current and design simplicity features of dynamic circuits. Simulation results show that DyCML circuits are superior to CMOS and DCVS logic styles in terms of power and delay. A 16 bit DyCML Carry Look Ahead Adder (CLA) fabricated in 0.6 /spl mu/m achieves a delay of 1.1 ns while dissipating 21.2 mW at 400 MHz.
4