A 45nm 8-core enterprise Xeon<sup>®</sup> processor

Abstract

A 2.3 B transistors, 8-core, 16-thread 64-bit Xeon® EX processor with a 24 MB shared L3 cache was implemented in a 45 nm 9-metal process. Multiple clock and voltage domains are employed to reduce power consumption. Long channel devices and cache sleep mode are used to minimize leakage. Core and cache recovery improve manufacturing yields and enable multiple product flavors using the same silicon die and package. The disabled blocks are both clock and power gated to minimize their power consumption. Idle power is reduced by shutting off the un-terminated I/O links and shedding phases in the voltage regulator to improve the power conversion efficiency.