A sub 2W low power IA Processor for Mobile Internet Devices in 45nm Hi-K metal gate CMOS

Abstract

This paper describes a low power Intelreg Architecture (IA) processor specifically designed for mobile internet devices (MID). The design consists of an in-order pipeline capable of issuing 2 instructions per cycle supporting 2 threads, 32 KB instruction and 24 KB data L1 caches, independent integer and floating point execution units, a 512 KB L2 cache and a 533 MT/s dual-mode (GTL and CMOS) front-side-bus (FSB). The design contains 47 million transistors in a die size under 25 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> manufactured in a 9-metal 45 nm CMOS process. Thermal design power (TDP) consumption is measured at 2 W, 1.0 V, 90degC using a synthetic power-virus test at a frequency of 1.86 GHz.