Impact of surface rouglmess on silicon and germanium ultra-thin-body MOSFETs

Abstract

Ultra-thin body (UTB) SOI MOSFET is promising for sub-50 nm CMOS technologies (ITRS, 2003). However, recent experimental finding by Uchida (2002) suggests the need for serious reconsiderations of its long-term scaling capability into the sub-10 nm body thickness (T/sub BODY/) regime. Two new phenomena attributed to surface roughness (SR) are identified by Uchida (2002); they are enhanced threshold voltage (V/sub TH/) shifts and drastic degradation of mobility with a T/sub BODY/ dependence according to Uchida (2002) and Sakaki (1934). In this work, we detail a study of these two phenomena in UTB MOSFETs with sub 10 nm T/sub BODY/ Si and Ge channels. Firstly, the phenomena of enhanced V/sub TH/ shifts is modeled by accounting for the fluctuation of quantized energy levels due to SR up to second order approximation. Good corroboration with experimental results by Uchida (2002) is obtained. Our model is then applied to examine the impact of enhanced VTn shifts on metal gate workfunction requirements. Secondly, we modeled the SR-limited electron and hole mobility and discuss their impact on the choice of surface orientations. Mobility anisotropy are also examined for the various surface orientations.