Low resistance Ti or Co salicided raised source/drain transistors for sub-0.13 μm CMOS technologies

Abstract

Raised source/drain (R/SD) CMOS transistors with Co or Ti salicide to improve narrow-poly sheet resistance and diode leakage are studied. At 0.11 /spl mu/m gate length, low resistance of 2 /spl Omega//sq and 1.2 /spl Omega//sq are achieved for CoSi/sub 2/ (with 400 /spl Aring/ R/SD) and TiSi/sub 2/ with 700 /spl Aring/ R/SD and pre-amorphization implant (PAI), respectively. These results are due to the lateral over-growth of the deposited silicon to form T-shaped gates. Significant improvement in the junction leakage current is also observed for the R/SD devices with CoSi/sub 2/ salicide. Comparison of integration issues such as silicide bridging, poly depletion, and gate oxide integrity are presented together with transistor drive current and source/drain series resistance.