50 nm gate-length CMOS transistor with super-halo: design, process, and reliability

Abstract

CMOS transistors with a 50 nm physical gate length are demonstrated. Super-halo, implemented by angle-tilted implantation, is utilized to control V/sub th/ roll-off down to a gate length of 40 nm. Super-halo also provides V/sub th/ adjustment as well as a retrograde channel to suppress subsurface body punch-through. 935 /spl mu/A//spl mu/m and 395 /spl mu/A//spl mu/m on-state drive currents were achieved for n- and p-channel MOSFETs, respectively, with a V/sub dd/ of 1.5 V. The I/sub drive//(C/sub ox(inv)/V/sub dd/) figure-of-merit (FOM) of the CMOS devices falls on the trend line extrapolated from existing industrial CMOS technologies. The impacts of super-halo on V/sub th/ roll-off, DIBL, gate overlap Miller capacitance and junction capacitance in a 50 nm MOSFET are investigated. Strong halo can result in drain-to-halo (body) band-to-band tunneling leakage even at room temperature. Degradation of gate oxide leakage and hot-carrier reliability due to large-angle-tilted halo implant are concerns in 50 nm CMOS transistors.