New protection techniques and test chip design for achieving high CDM robustness

Abstract

CDM protection techniques for two important circuits are developed. In the first protection dummy logic circuits are added for separated small power domains. The dummy logic circuit can assist parallel-connected ESD protection devices to discharge CDM current at the initial discharge phase of the CDM event. The second protection technique for input gate protection is to use the stack-structured input circuits by employing dual diode ESD protection method. Also, a new CDM TEG chip design that can be directly evaluated by CDM zapping test is presented.