Publication | Closed Access
Impact of process scaling on 1/f noise in advanced CMOS technologies
38
Citations
7
References
2002
Year
Unknown Venue
Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignSv/sub Gate/Advanced Cmos TechnologiesTechnology ScalingElectronic EngineeringSubstrate DopeBias Temperature InstabilityMixed-signal Integrated CircuitComputer EngineeringNoiseItrs RoadmapMicroelectronicsElectronic Circuit
The influence of the gate-oxide thickness, the substrate dope, and the gate bias on the input-referred spectral 1/f noise density Sv/sub gate/ has been experimentally investigated. It is shown that the dependence on the oxide thickness and the gate bias can be described by the model of Hung, and that Sv/sub gate/ can be predicted for future technologies. Discrepancies with the ITRS roadmap are discussed.
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