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Fully-depleted strained-Si on insulator NMOSFETs without relaxed SiGe buffers
18
Citations
8
References
2004
Year
Unknown Venue
Materials EngineeringElectrical EngineeringEngineeringSige Buffer LayerNanoelectronicsStress-induced Leakage CurrentBias Temperature InstabilityApplied PhysicsSige LayerSi N-channel MosfetsSemiconductor Device FabricationRelaxed Sige BuffersMicroelectronicsSilicon On InsulatorSemiconductor Device
Fully-depleted strained Si n-channel MOSFETs were demonstrated on a compliant borophosphorosilicate insulator (BPSG) without an underlying SiGe buffer layer. Stress balance of a SiGe/Si structure, transferred onto BPSG by wafer bonding and Smart-cut processes, is utilized for the first time to make strained-Si on insulator (sSOI) by a process that does not involve the introduction of misfit dislocations. Strained-Si n-channel MOSFETs with a strain level of 0.6%, equivalent to that of a conventional strained Si layer grown on a relaxed Si/sub 0.85/Ge/sub 0.15/ buffer, exhibit 60% mobility enhancement over the control, in good agreement with theory. This approach to fabricating strained Si overcomes any potential process or device complexity due to the presence of a SiGe layer in the final devices.
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