Thin, fully depleted monolithic active pixel sensor based on 3D integration of heterogeneous CMOS layers

Abstract

On the way towards fast, radiation tolerant and ultra thin CMOS radiation sensors, we propose new generation of devices based on commercial availability of vertical integration of several CMOS wafers (3D Electronics). In this process, each wafer may be thinned down to about 10 microns end equipped with through-silicon vias (TSV) allowing for electrical interconnection between wafers at a very small pitch (few microns) and with a minimum material budget. The proposed prototype device is a 245×245 pixel array with a pitch of 20 ¿m, providing active area of 5×5 mm2. In the first silicon layer charge sensing diode and first stage buffer amplifier (source follower) are integrated, using CMOS process on high resistivity epitaxial wafers. Outputs of buffer voltage amplifiers are vertically coupled (through a poly-poly capacitor) to the following stage of processing electronics (charge integration, time continuous shaping and signal discrimination), placed in the second silicon layer (0.13 micron CMOS). The third silicon layer (also 0.13 micron CMOS) is used for implementation of digital (binary) readout with a fast, data driven, self-triggering data flow. After description of the proposed 3D device, an update of results from ongoing tests with the first CMOS MAPS prototype fabricated using high-resistivity epitaxial substrate is provided.