Scaling analysis of phase-change memory technology

Abstract

The scaling capability of chalcogenide-based phase-change memory (PCM) is discussed. Experimental and numerical results are presented, showing that the reset current scales down with the device contact area, reaching values as low as 50 /spl mu/A. The impact of thermal cross-talk between adjacent bits is investigated, showing that thermal disturbs will not limit the scaling of PCM down to the 65 nm technology node. Finally, scaling rules for the PCM technology are provided.