SPOTEC-a sub-10- mu m/sup 2/ bipolar transistor structure using fully self-aligned sidewall polycide base technology

Abstract

A novel structure for high-speed Si bipolar transistors has been developed and a 9.4- mu m/sup 2/ transistor is demonstrated. Transistors are fabricated with a new sidewall polycide base electrode technology (SPOTEC), narrow W plug metallization, narrow U-groove isolation, and 0.3- mu m lithography using an e-beam direct writing technique. SPOTEC is used to reduce the base electrode area. That is, CVD (chemical vapor deposited) W is selectively deposited on a sidewall surface of the polysilicon and is silicided. This technology makes a narrow and low-resistance base electrode (0.4 mu m wide and 10 Omega / Square Operator ) possible. The collector electrode is directly contacted on an n/sup +/ buried layer to reduce its area. The contact hole is filled with a low-resistance W plug by using selective W CVD technology. To reduce the isolation area, a narrow, deep U-groove is etched and refilled with CVD SiO/sub 2/. These four key techniques reduce the transistor area to less than 10 mu m/sup 2/. The shallow E-B junctions are formed using low-energy ion implantation and RTA (rapid thermal annealing). A high cutoff frequency of 38 GHz and small junction capacitances are obtained.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>