Symposium on Integrated Circuits and Systems Design · 1998 · 37 citations · 10 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureField-programmable Gate ArraysReconfigurable ComputingAccelerator ArchitectureConfiguration MemoryField-programmable Gate Array ArchitectureHardware AccelerationMemory Subsystem DesignReconfigurable System ArchitectureCompressionProcessor ArchitectureReconfigurable ArchitecturesReconfigurable Array ArchitectureReconfigurable Hardware ArchitectureReconfigurable Processor ArchitecturesRisc ArchitecturesVideo Compression
We describe the MorphoSys reconfigurable system, which combines a reconfigurable array of processor cells with a RISC processor core and a high bandwidth memory interface unit. We introduce the array architecture, its configuration memory, inter-connection network, role of the control processor and related components. Architecture implementation is described in brief and the efficacy of MorphoSys is demonstrated through simulation of video compression (MPEG-2) and target-recognition applications. Comparison with other implementations illustrates that MorphoSys achieves higher performance by up to 10X.
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Building and using a highly parallel programmable logic array
Maya Gokhale, William T. Holmes, A. Kopser et al. · Computer · 1991 · 202 citations