10th Annual IEEE (GaAs IC) Symposium, Gallium Arsenide Integrated Circuit. Technical Digest 1988. · 2003 · 11 citations · 0 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignDigital Integrated Circuit DesignDigital Integrated CircuitsHigh-frequency Semiconductor DevicesIntegrated Circuit DesignRadio-frequency Integrated CircuitsComplementary Metal-oxide-semiconductor LogicDirect Digital SynthesisDirect SynthesisLogic GatesLow-power Standard Cell DesignPipelined Digital CircuitsRadio-frequency Integrated Circuit DesignRf Cmos Design
The authors described the design and implementation of a 1.25-GHz 26-bit pipelined accumulator. The chip was implemented using capacitor diode-coupled FET logic (CDFL), employing the planar GaAs depletion mode process. Performance equivalent to that of a fully custom design was achieved with a standard cell design approach. Fully functional chips have been fabricated and operated at 1.25 GHz with 2.6 W total power dissipation. The accumulator chip is 4.6 mm*3.9 mm and contains approximately 2000 equivalent logic gates. It is concluded that this device is suited for use in direct digital synthesis (DDS) and signal-processing applications. In particular, the results obtained demonstrate that DDS systems of up to 500-MHz bandwidths are possible.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>