Analysis and Design of Power Harvesting Circuits for Ultra-Low Power Applications

Abstract

This paper presents an analytical model for power harvester circuits used in Ultra-low power applications. Assuming that the MOS devices of the circuit fully operate in the Sub-threshold regime in both forward and reverse regions, closed-form equations for important properties of the rectifier circuit such as output voltage, efficiency and input resistance are derived. The model includes the effect of the compensation voltage on the circuit behavior. There is a good agreement between the simulation results and the model. In addition, the contour plots needed to simultaneously optimize the matching network and the rectifier circuit are derived by the resulting equations. A 50-Stage rectifier was fabricated in a 180-nm standard CMOS Process. The proposed model is verified with the measurement results. The model has a maximum error of 10% in comparison with the circuit simulation, and a maximum error of 12% with the measured values.