Design productivity of a high level synthesis compiler versus HDL

TLDR

Hardware system complexity is growing faster than designer productivity, creating a Design Productivity Gap that inflates design costs. The paper defines Design Productivity and introduces a metric to compare HLS methods with manual hardware description. The metric evaluates the trade‑off between design efficiency and implementation quality and is applied to compare a CAPH‑based HLS compiler with manual VHDL writing. The study shows a 2.3× productivity gain for the CAPH HLS method, driven by a 4.4× faster design time but a 1.9× reduction in quality, and discusses why VHDL is lower level than CAPH.

Abstract

The complexity of hardware systems is currently growing faster than the productivity of system designers and programmers. This phenomenon is called Design Productivity Gap and results in inflating design costs. In this paper, the notion of Design Productivity is precisely defined, as well as a metric to assess the Design Productivity of a High-Level Synthesis (HLS) method versus a manual hardware description. The proposed Design Productivity metric evaluates the trade-off between design efficiency and implementation quality. The method is generic enough to be used for comparing several HLS methods of different natures, opening opportunities for further progress in Design Productivity. To demonstrate the Design Productivity evaluation method, an HLS compiler based on the CAPH language is compared to manual VHDL writing. The causes that make VHDL lower level than CAPH are discussed. Versions of the sub-pixel interpolation filter from the MPEG HEVC standard are implemented and a design productivity gain of 2.3× in average is measured for the CAPH HLS method. It results from an average gain in design time of 4.4× and an average loss in quality of 1.9×.