A Novel Dicing Technologies for WLCSP Using Stealth Dicing through Dicing Tape and Back Side Protection-Film

Abstract

Market demand of IC package for communication is increasing along with the popularization of mobile type of information and communication devices. Wafer Level Chip Scale Package (WLCSP) is popular method for above mentioned devices from production cost point of view and is widely used for this kind of mobile devices. There are two requirements for the WLCSP nowadays. One is a cost reduction, the other is a solution to package crack. The main idea of a cost reduction is a dicing street reduction. The dicing street reduction leads to the increasing the number of die per wafer (die gross) that means a reduction of production cost. We select a "Stealth dicing" process. SD process is expected to increase the number of die that can be obtained from a wafer compared to normal dicing because it is possible to make the necessary street width (cut width) narrower. Almost WLCSPs are typically mounted on board with only solder joint, without under fill and so solder joint reliability is a prime concern. Especially side walls of WLCSP are not covered with protection material like under fill, so mechanical damage on side walls caused by dicing process leads to package crack at Thermal Cycle Test (TCT). This side wall damage and cracks are serious problem recently. SD process might avoid this side wall crack also. In this paper, we propose a novel dicing technologies for WLCSP using stealth dicing through dicing tape and back side protection-film that can make the necessary street width (cut width) narrower that means street reduction and avoid the package crack of TCT and the drop test.