Ultralow ON-Resistance SOI LDMOS With Three Separated Gates and High-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math> </inline-formula> Dielectric

Abstract

A novel ultralow specific on-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> ) SOI lateral double-diffused MOS (LDMOS) with three separated gates (TSGs) and high-k (HK) pillars is proposed and investigated by simulation. The TSGs include the planar gate (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub> ), the segmented trench gate (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Y</sub> ) between the p+ body contact regions, and the embedded trench gate (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Z</sub> ) connected with HK pillars and p-well regions. First, in the on-state, the TSGs form three channels, including one lateral channel and two vertical channels, which can decrease R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> significantly. Second, G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Y</sub> and G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Z</sub> are extended to the buried oxide, widening the vertical conduction area and enhancing the current density in the bulk to further reduce RON,sp. Furthermore, the electron accumulation layer (EAL) is formed not only beside the extended G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Y</sub> and G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Z</sub> , but also along the sidewall of the drift region near the source side, thus reducing R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> greatly. Third, the HK pillars can increase the optimal drift doping concentration (Nd) to decrease R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> owing to the assisted depletion effect. The device obtains an ultralow R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> of 0.34 mΩ · cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at BV = 97 V. Compared with the conventional LDMOS and other previous devices, the TSG-HK LDMOS achieves better tradeoff between the breakdown voltage and R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> .