Concepedia

A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs

Manuel J. Barragán, Asma Laraba, Haralampos‐G. Stratigopoulos, Salvador Mir, Hervé Le-Gall, Hervé Naudet

Journal of Electronic Testing · 2016 · 14 citations · 16 references

Open access

References

16

Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization

Christian Enz, Gábor C. Temes · Proceedings of the IEEE · 1996 · 1.8K citations · Full text

Engineering, Electrical Engineering, Analog Electronics +16

Analysis of switched-capacitor common-mode feedback circuit

Ojas Choksi, L.R. Carley · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 2003 · 169 citations

Engineering, Electrical Engineering, Analog Electronics +16

A BIST scheme for on-chip ADC and DAC testing

Jiun-Lang Huang, Chee-Kian Ong, Kwang‐Ting Cheng · 2000 · 149 citations

Engineering, Computer Engineering, Electrical Engineering +17

On-chip ramp generators for mixed-signal BIST and ADC self-test

B. Provost, E. Sánchez‐Sinencio · IEEE Journal of Solid-State Circuits · 2003 · 146 citations

Engineering, Computer Engineering, Electrical Engineering +17

Oscillation built-in self test (OBIST) scheme for functional and structural testing of analog and mixed-signal integrated circuits

K. Arabi, Bożena Kamińska · 2002 · 129 citations

Engineering, Computer Engineering, Electrical Engineering +17