IACR Cryptology ePrint Archive · 2012 · 63 citations · 14 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureCryptographyField-programmable Gate ArraysAlgorithm AnalysisCryptographic HashingField-programmable Gate Array ArchitectureFpga ArchitectureHardware AccelerationHash FunctionsArchitectural ExplorationArea EfficiencyArea Ratio DesignArea-efficient Fpga ArchitectureCryptographic Accelerator DesignHardware Acceleration For CryptographyHardware Performance ModelingHash Table Performance Analysis
In this paper we present a comprehensive comparison of all Round 3 SHA-3 candidates and the current standard SHA-2 from the point of view of hardware performance in modern FPGAs. Each algorithm is implemented using multiple architectures based on the concepts of iteration, folding, unrolling, pipelining, and circuit replication. Trade-offs between speed and area are investigated, and the best architecture from the point of view of the throughput to area ratio is identified. Finally, all algorithms are ranked based on their overall performance in FPGAs. The characteristic features of each algorithm important from the point of view of its implementation in hardware are identified.
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FPGA Implementations of the Round Two SHA-3 Candidates
Brian Baldwin, Andrew W. Byrne, Liang Lu et al. · 2010 · 95 citations
Stefan Tillich, Martin Feldhofer, Mario Kirschbaum et al. · IACR Cryptology ePrint Archive · 2009 · 50 citations