Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier

Abstract

This brief proposes the design of a low-voltage static random access memory (SRAM) for biomedical chip applications. The SRAM is designed using a standard 8T bit cell, featuring a shared data-aware write scheme and a differential reference-based sense amplifier. The proposed techniques make it possible for the 8T SRAM to use bit-interleaving architecture and address the half-select problem, achieving area efficiency and power reduction. A 96-kb 8T SRAM test chip is implemented in a 65-nm CMOS process to verify the proposed schemes, which operates functionality at a VDD <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> of 0.36 V and has a power consumption of 5.1 μW.