Xiaoyang Zeng - Concepedia

Author

Xiaoyang Zeng

Fudan University ORCID

Also Known As

X. Zeng, Xiao-Yang Zeng, Xiao-yang Zeng, Xiaoyang ZENG, Xiaoyang Zeng, Xiujuan Zeng, Zeng, X., Zeng, Xiaoyang

113

Publications

562

Citations

H-Index

Concepts

All Affiliations

Fudan University State Key Laboratory of ASIC and System Chinese Academy of Sciences Institute of Microelectronics Shanghai Fudan Microelectronics (China)

About

Xiaoyang Zeng is an author at Fudan University specializing in engineering, computer engineering, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	11	12	325
2	Computer Engineering	10	11	297
3	Electrical Engineering	9	9	273
4	Computer Science	5	5	77
5	Systems Engineering	1	1	28

Xiaoyang Zeng

Publications

380

Citations

H-Index

Page 1

	Year	Citations
An Energy-Efficient Design for ECG Recording and R-Peak Detection Based on Wavelet Transform Yao Zou, Jun Han, Sizhong Xuan, IEEE Transactions on Circuits & Systems II Express Briefs Medical ElectronicsMedical MonitoringR-peak DetectionEngineeringWavelet Transform	2014	78
Subthreshold Level Shifter With Self-Controlled Current Limiter by Detecting Output Error Liang Wen, Xu Cheng, Shudong Tian, IEEE Transactions on Circuits & Systems II Express Briefs Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignData Converter	2015	56
Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier Liang Wen, Xu Cheng, Keji Zhou, IEEE Transactions on Circuits & Systems II Express Briefs Non-volatile MemoryEngineeringVlsi DesignEmerging Memory TechnologyBit-interleaving-enabled 8T	2016	38
Robust Timing and Frequency Synchronization Scheme for DTMB System Jianming Wu, Yun Chen, Xiaoyang Zeng, IEEE Transactions on Consumer Electronics EngineeringClock RecoveryTiming AnalysisRobust TimingDtmb System	2007	28
Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability Liang Wen, Zhikui Duan, Yi Li, Microelectronics Journal	2014	23
A 28nm 1.5Mb Embedded 1T2R RRAM with 14.8 Mb/mm<sup>2</sup> using Sneaking Current Suppression and Compensation Techniques Jianguo Yang, Xiaoyong Xue, Xiaoxin Xu, Electrical EngineeringEngineeringReliable ReadPmos SelectorEmerging Memory Technology	2020	22
An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications Keji Zhou, Chenyang Zhao, Jinbei Fang, IEEE Transactions on Circuits & Systems II Express Briefs EngineeringNeural NetworkHardware AlgorithmComputer ArchitectureParallel Computing	2021	22
Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction Liang Wen, Yuejun Zhang, Xiaoyang Zeng IEEE Transactions on Very Large Scale Integration (VLSI) Systems Hardware SecurityNon-volatile MemoryElectrical EngineeringMemory ArchitectureEngineering	2019	16
ARBiS: A Hardware-Efficient SRAM CIM CNN Accelerator With Cyclic-Shift Weight Duplication and Parasitic-Capacitance Charge Sharing for AI Edge Application Chenyang Zhao, Jinbei Fang, Jingwen Jiang, IEEE Transactions on Circuits and Systems I Regular Papers Artificial IntelligenceEngineeringMachine LearningComputer ArchitectureHigh-performance Architecture	2022	16
A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS Haozhe Zhu, Chixiao Chen, Shiwei Liu, IEEE Journal on Emerging and Selected Topics in Circuits and Systems EngineeringCommunication-aware Dnn AcceleratorHardware AlgorithmComputer ArchitectureIntegrated Circuits	2020	14

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