High Performance Unannealed a-InGaZnO TFT with an Atomic-Layer-Deposited SiO2 Insulator

Abstract

Amorphous In-Ga-Zn-O (a-IGZO) thin-film transistor with an atomic-layer-deposited (ALD) SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate insulator was fabricated under a maximum processing temperature of 250 °C and compared with the counterpart with a plasmaenhanced chemical vapor deposited (PECVD) SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate insulator. It was demonstrated that the ALD SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> insulator could generate much better device performance than the PECVD one. This is attributed to a lower density of interfacial traps, weaker surface roughness scattering, and enhanced passivation of oxygen vacancies in the a-IGZO channel atop the ALD SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> film with more OH groups. Without the need of post-annealing, the ALD SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> device exhibited very good stability under a negative gate bias stress (-15 V), while maintaining superior performance such as quite high field effect mobility of 63.6 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> , a low threshold voltage of -0.10 V, a small subthreshold swing of 0.14 V/decade, and a large ON/OFF current ratio of ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> .