III–V Tunnel FET Model With Closed-Form Analytical Solution

Abstract

Using an idealized semianalytical model of charge transport for InAs-based tunneling FET, it is shown that the output and transfer characteristics can be accurately reproduced and could be used to develop compact models. The use of a mathematical approximation for the analytical solution of the surface potential is vital here to minimize the computation time. The 20-nm gate homojunction and 40-nm gate heterojunction transistors have been simulated and compared with the calibrated numerical simulation results. The results are in good agreement.