A new one-transistor, one-capacitor RAM cell structure called a Quadruply Self-Aligned Stacked High Capacitance (QSA SHC) RAM is proposed as a basic cell for a future one-million-bit VLSI memory. This cell consists of a QSA MOSFET and a Ta 2 O 5 capacitor stacked on it. By this cell, the ultimate cell area 3F \times 2F can be realized with sufficient operating margin. Here, F is the minimum feature size. The basic cell was fabricated and its operation was experimentally verified. The leakage current of Ta 2 O 5 film was small enough for the storage capacitor dielectric. Using a 3F \times 4F cell and a 4F pitch sense amplifier, a one-million-bit memory was designed with a 2-µm rule. A cell size of 6.5 × 8 µm ² , and a chip size of 9.2 × 9.5 mm ² were obtained. The access time, neglecting the RC time constant of the word line, was estimated to be about 170 ns. Based on this design, it is argued that a future one-million-bit memory can be realized by QSA SHC technology with a 2-1-µm process. The mask set of the 1-Mbit RAM was actually fabricated by an electron-beam mask maker. A photomicrograph of the 1-Mbit RAM chip patterned by the mask set is shown. This chip was patterned not to get an operating sample but to show an actual chip image of the future 1- Mbit RAM. The area of each circuit block including storage array can be seen in this chip image.

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