High-speed time interleaved ADCs

Abstract

Software-defined multi-gigahertz receivers require high-speed ADCs at the frontend. Time interleaving has emerged as the most common method of achieving ultra-fast quantization at reasonably high resolution. However, this multi-path solution introduces systematic errors due to mismatches in signal paths, whereas in non-interleaved versions these were mixed to DC, where they appeared as a harmless offset. Mitigating all possible time-interleaved errors comes at a heavy cost in complexity, risk, and power. Knowing which errors are most important and which can be neglected in any given application is essential for picking an appropriate architecture and calibration scheme. Guidelines for reducing errors lead to potentially different architecture choices. When the goal is to use the fewest slices, an inerleaved pipelined ADC results, whereas when the overriding objective is to use the simplest slice possible, a large array of SAR slices is usually adopted. Both approaches have merit. This article addresses when and where to use each approach by discussing specification requirements and showing that different types of error sources should not be merged into one single metric like ENOB, but should be treated separately to determine their impact on overall system performance. An example of an eight-way interleaved pipelined ADC is presented, which illustrates these principles in the context of a real circuit.