Temperature Dependence of MCU Sensitivity in 65 nm CMOS SRAM

Abstract

The temperature dependence of single-event upset multiplicity in 65 nm CMOS SRAM was investigated in this paper. Experimental results show significant increase of upset multiplicity over a temperature range of 300 to 400 K. Main physical mechanisms leading to the increase of the multiplicity of upsets at elevated temperatures were studied using three-dimensional (3-D) device simulations. A major role of upset voltage decrease and temperature dependence of the parasitic bipolar effect was established. Simulation results can be used for maximal upset multiplicity estimation.