IEEE Journal of Solid-State Circuits · 2016 · 67 citations · 32 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsVlsi DesignClock ManagementCmos Circuit DesignDc-dc ConvertersIntegrated Circuit DesignLow-power Digital Circuit DesignVoltage ScalingClocking ArchitectureConversion LossDynamic ScalingLow-power MicroarchitecturePower Conversion EfficiencyRipple ReductionRisc-v Core DesignSwitched-capacitor Converters
This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC-DC switches, DC-DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.
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A dynamic voltage scaled microprocessor system
Tom Burd, Trevor Pering, A. Stratakos et al. · IEEE Journal of Solid-State Circuits · 2000 · 911 citations
Richard M. Russell · Communications of the ACM · 1978 · 697 citations · Full text
28nm FDSOI technology platform for high-speed low-voltage digital applications
N. Planes, O. Weber, V. Barral et al. · 2012 · 424 citations
Engineering, Computer Engineering, Electrical Engineering +16