A configurable radiation tolerant dual-ported static RAM macro, designed in a 0.25 $\mu$m CMOS technology for applications in the LHC environment

Abstract

A configurable dual-port SRAM macro-cell has been developed based on a commercial, 0.25 m, 3 metal layer, CMOS technology.Well-established radiation tolerant layout techniques have been employed in order to achieve the total dose hardness levels required for the LHC experiments.The presented SRAM macro-cell can be used as a building block for on chip readout pipelines, data buffers and FIFOs.The design features synchronous operation with separate address and data busses for the read and write ports, thus allowing the execution of simultaneous read and write operations.The macro-cell is configurable in terms of word counts and bit organization.This means that tiling memory blocks into an array and surrounding it with the relevant peripheral blocks can construct a memory of arbitrary size.Circuit techniques used for achieving macro-cell scalability and low power consumption are presented.To prove the concept of the macro-cell scalability two demonstrator memory chips of different sizes were fabricated and tested.The experimental test results are being reported.