EngineeringComputer EngineeringComputer ArchitectureLow-power DesignSystem-on-chip DesignClock Distribution NetworksClock ManagementClock SynchronizationData SynchronizationDelay ModelingTiming AnalysisClock DesignClock Network ArchitectureClocking ArchitectureCycle TimeCycle Time AnalysisHigh PerformanceSynchronizationSynchronizers
Delay variations are typically accounted for by increasing cycle time margins. Adaptive synchronization eliminates this on inter-modular interfaces in very large, high performance chips. The chip is divided into multiple smaller synchronous modules. Multi-synchronous hierarchical clocking provides the same frequency to all modules, but does not maintain any particular phase. Adaptive synchronizers adapt to the time-varying inter-modular clock and data phases, and out-perform conventional synchronizers.