A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS

Abstract

This paper describes the implementation of a 4-level pulse-amplitude-modulation (4-PAM) receiver consisting of a 6-bit time-interleaved successive-approximation analog-to-digital converter (TI-SAR ADC), followed by a fully digital speculative 2-tap decision-feedback equalizer (DFE) operating at one-fourth of the modulation rate. The receiver, implemented in an experimental chip fabricated in 32 nm SOI CMOS, is designed to recover data at 56Gb/s over a channel with an attenuation of 11 dB at 14 GHz. The power consumption of the receiver is 202.7 mW at a supply of 1.2 V, achieving an overall energy efficiency of 3.62 pJ/b. The DFE along with area-optimized register arrays and memory-control buffers occupies an area of 0.154×0.169 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Experimental results demonstrating a BER<;10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-8</sup> are obtained using a (2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> -1)-bit pseudo-random binary sequence (PRBS-7).