Fully functional perpendicular STT-MRAM macro embedded in 40 nm logic for energy-efficient IOT applications

Abstract

We present for the first time a fully functional 40 nm perpendicular STT-MRAM macro (1 Mb, ×32/×64 IO) embedded into a foundry standard CMOS logic platform. We achieved target design specifications of 20 ns read access time and 20–100 ns write cycle time without redundancy repair at standard core and IO voltages. The full 1 Mb macro can be switched reliably with write pulse as short as 6 ns, which results in full-chip write power of ∼ 3.2 μW/Mbps at ×64. This is the lowest eNVM write power reported at a full-chip level and about three orders of magnitude smaller than that of eFLASH. The 0.5 Mbit high-density bitcell array also demonstrates good Rp distribution and 100 % STT switching. Our results demonstrate superior power-area-feature attributes of perpendicular STT-MRAM as a best-in-class unified eNVM solution for Internet-of-Things (IOT) applications at 40 nm as well as the scalability of these advantages to 28 nm and beyond.