17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization

Abstract

The power consumption of a mobile application processor (AP) is strongly limited by the SRAM minimum operating voltage, VMIN [1], since the 6T bit cell must balance between write-ability and bit cell stability. However, the SRAM VMIN scales down gradually with advanced process nodes due to increased variability. This is evident with the quantized device-width and limited process-knobs of a FinFET technology, which has greatly affected SRAM design [2–4]. Therefore, assist-circuits are more crucial in a FinFET technology to improve VMIN, which in turn adds to the Power, Performance, and Area (PPA) gain of SRAM.