2015 · 111 citations · 1 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsNanotechnologySemiconductor DevicesCmos Circuit DesignDevice ScalingIntegrated Circuit DesignMemory DevicesMetal-oxide-semiconductor Field-effect TransistorsNanoelectronics3D Nand ArchitectureDevice Scaling EffectsMemory Circuit DesignMoore's Law ScalingThree-dimensional Device Scaling
NAND Flash has followed Moore's law of scaling for several generations. With the minimum half-pitch going below 20nm, transition to a 3D NAND cell is required to continue the scaling. This paper describes a floating gate based 3D NAND technology with superior cell characteristics relative to 2D NAND, and CMOS under array for high Gb/mm2 density.
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