Modeling and design solutions to overcome warpage challenge for fan-out wafer level packaging (FO-WLP) technology

Abstract

Fan-out wafer-level-packaging (FO-WLP) technology gets more and more significant attention with its advantages of small form factor, higher I/O density, cost effective and high performance for wide range application. However, wafer warpage is still one critical issue which is needed to be addressed for successful subsequent processes for FO-WLP packaging. In this study, methodology to reduce wafer warpage of 12" wafer at different processes was proposed in terms of geometry design, material selection, and process optimization through finite element analysis (FEA) and experiment. Wafer process dependent modeling results were validated by experimental measurement data. Solutions for reducing wafer warpage were recommended. Key parameters were identified based on FEA modeling results: thickness ratio of die to total mold thickness, molding compound and support wafer materials, dielectric material and RDL design.