17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology

Abstract

System-on-Chip (SoC) designs contain a variety of IP blocks which use multiport memories to improve performance by enabling multiple simultaneous operations in the same memory bank. Conventional 2-read/write 8T dual-port SRAMs (2RW) suffer from read and write disturb issues when both wordlines in one row are activated at the same time. 1-read, 1-write 8T decoupled dual port cells (1R1W) eliminate read disturb by preventing charge-sharing with internal storage nodes while the read wordline (RDWL) is activated. Dummy-read disturb can also be prevented in 1R1W arrays by using a non-interleaved design.