12.2 A 94.6%-efficiency fully integrated switched-capacitor DC-DC converter in baseline 40nm CMOS using scalable parasitic charge redistribution

Abstract

This work introduces a scalable parasitic charge-redistribution technique that is able to significantly increase the efficiency of integrated SC converters. A circuit has been fabricated in a 40nm baseline CMOS process that demonstrates the presented technique and advances the state-of-the-art by achieving a very high efficiency for fully-integrated SC converters of 94.6%.