Optimal design of new cascade multilevel converter topology based on series connection of extended sub‐multilevel units

Abstract

In this study, a new circuit for cascade multilevel converter based on series connection of extended sub‐multilevel units is described. In order to produce all levels at output voltage waveform, an algorithm is proposed to determine the values of dc sources. To maximise the number of output voltage levels with minimum number of utilised power electronic components, the proposed cascade multilevel converter is optimised. The comparison results with other recently presented topologies are provided in terms of the number of utilised components and standing voltage on switches. Compared to other structures, the proposed topology utilises fewer number of insulated‐gate bipolar transistors, drivers, anti‐parallel diodes, and dc sources. Also, the value of standing voltage of switches in the recommended topology is low. Experimental results for proposed converter are provided to verify the operation of presented structure.