21st Design Automation Conference Proceedings · 1984 · 26 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureMicroelectronicsSemiconductor DevicesHardware Fault ToleranceHierarchical DesignIntegrated Circuit DesignIntegrated Circuit DevicesMemory Hierarchy DesignVery-large-scale Integration LayoutChip PartitioningCompact Device DesignLayout TechniquesThree-dimensional Integrated Circuit Layout
This paper describes a compactor that is practical for compacting whole chips that are designed hierarchically, and can produce a reasonable result in spite of the layout being over-constrained. The layout produced is good enough to be used in high volume chips. The compactor is currently used in a cell layout system and a chip assembly tool.
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