2004 · 38 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsCalibrationCmos Circuit DesignDistortion AnalysisLow-noise Circuit DesignLow-power Digital Circuit DesignAnalog-to-digital Converter DesignCalibration Techniques For Analog CircuitsDigital-to-analog Converter DesignDynamic Power DissipationSlew-rate DistortionSmall-signal Gain
A 12 b 80 MS/s pipelined ADC is calibrated for constant and signal-dependent gain errors as well as for slew-rate errors. With foreground calibration, peak SNDR is 72.6 dB, and peak SFDR is 85.4 dB. Using an on-chip microprocessor for calibration, the total power dissipation is 755 mW from 2.5 V, and the active area is 19.6 mm/sup 2/ in a 0.25 /spl mu/m CMOS process.
6
A 12 b 65 MSample/s CMOS ADC with 82 dB SFDR at 120 MHz
L. Singer, Stacy Ho, M. Timko et al. · 2002 · 86 citations
Engineering, Computer Engineering, Electrical Engineering +17