Digital background calibration of an algorithmic analog-to-digital converter using a simplified queue

Abstract

An analog queue-based architecture and an adaptive digital-calibration algorithm calibrate an 8-bit two-stage pipelined algorithmic analog-to-digital converter. To minimize power dissipation and noise, the queue consists of only one sample-and-hold amplifier. At a sampling rate of 20 Msamples/s, the peak signal-to-noise-and-distortion ratio is 45 dB, and the spurious-free dynamic range is 62 dB. The total power dissipation is 25.4 mW from 3.0 V. The active analog area is 0.11 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .