A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver

Abstract

An 8-Gb/s 0.3-/spl mu/m CMOS transceiver uses multilevel signaling (4-PAM) and transmit pre-shaping in combination with receive equalization to reduce ISI due to channel low-pass effects. High on-chip frequencies are avoided by multiplexing and demultiplexing the data directly at the pads. Timing recovery takes advantage of a novel frequency acquisition scheme and a linear PLL with a loop bandwidth >30 MHz, phase margin >48/spl deg/ and capture range of 20 MHz without a frequency acquisition aid. The transmitted 8-Gbps data is successfully detected by the receiver after a 10-m coaxial cable. The 2 mm/spl times/2 mm chip consumes 1.1 W at 8 Gbps with a 3-V supply.