A single-chip 10 Gb/s transceiver LSI using SiGe SOI/BiCMOS

Abstract

A fully-integrated single-chip SiGe SOI/BiCMOS transceiver LSI for 10 Gb/s applications combines 4b FIFO, 10 GHz PLL, 16:1 MUX, 10 Gb/s input data decision circuit, clock and data-recovery circuit, 1:16 DeMUX, data loop back function, and self-testing using 2/sup 23/-1 PRBS generator. The die is 5.6/spl times/5.3 mm/sup 2/ and consumes 2.6 W from 3.3/2.5 V.