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Co-integration of InGaAs n- and SiGe p-MOSFETs into digital CMOS circuits using hybrid dual-channel ETXOI substrates
37
Citations
9
References
2013
Year
Unknown Venue
EngineeringDevice IntegrationDigital Cmos CircuitsIntegrated CircuitsInterconnect (Integrated Circuits)Semiconductor DeviceHybrid SubstratesNanoelectronicsMixed-signal Integrated CircuitIntegrated Circuit DesignSige P-mosfetsIngaas LayersElectrical EngineeringComputer EngineeringSemiconductor Device FabricationMicroelectronicsThree-dimensional Heterogeneous IntegrationApplied PhysicsDense Co-integrationBeyond CmosOptoelectronics
We demonstrate for the first time a dense co-integration of co-planar nano-scaled SiGe p-FETs and InGaAs n-FETs. This result is based on hybrid substrates containing extremely-thin SiGe and InGaAs layers on insulators (ETXOI). We first show that such hybrid substrates can be fabricated by direct wafer bonding with stacked high-mobility layers thinner than 8nm. A process flow is presented that allows us to fabricate n- and p-channel field effect transistors with ultra-thin body and BOX (UTBB-FET) on the same wafer. Gate lengths down to 40nm produced at sub-μm gate-pitch are achieved. Working CMOS inverters are obtained using a common front-end which confirms the viability of this integration scheme for hybrid high-mobility dual-channel CMOS. We also highlight that back-biasing technique for V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> tuning can still be used despite the dualchannel structure, as implemented in standard ETSOI circuits.
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