Altitude SEE Test European Platform (ASTEP) and First Results in CMOS 130 nm SRAM

Abstract

The "altitude SEE test European platform" (ASTEP) is dedicated to real-time soft-error rate (SER) testing of semiconductor memories. The platform, located in the French Alps on the "Plateau de Bure" at 2552 m, has been operational since March 2006. This test facility includes a proprietary automatic test equipment specially designed for static memory (SRAM) testing and secured remote control operation via internet. First real-time SER measurements on 3.6 Gbit of SRAMs manufactured in CMOS 130 nm technology are reported, as well as the comparison between real-time and accelerated SER. Project perspectives for CMOS 65 nm SRAMs are finally reported.