CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging

TLDR

Hardware verification is hampered by nondeterminism arising from uninitialized state, I/O, and timing variations on high‑speed buses, which cause different behavior on successive runs from the same initial state. The authors aim to eliminate this nondeterminism entirely to improve hardware debugging. They propose CADRE, a cycle‑accurate deterministic replay architecture that introduces a novel scheme for deterministic communication on source‑synchronous buses crossing clock‑domain boundaries, enabling board‑level determinism. Experiments on a 4‑way multiprocessor server demonstrate that CADRE achieves cycle‑accurate deterministic execution for one‑second intervals with only ~200 MB of buffering and ~1 % performance overhead, while imposing modest hardware requirements.

Abstract

One of the main reasons for the difficulty of hardware verification is that hardware platforms are typically nondeterministic at clock-cycle granularity. Uninitialized state elements, I/O, and timing variations on high-speed buses all introduce nondeterminism that causes different behavior on different runs starting from the same initial state. To improve our ability to debug hardware, we would like to completely eliminate nondeterminism. This paper introduces the cycle-accurate deterministic replay (CADRE) architecture, which cost-effectively makes a board-level computer cycle-accurate deterministic. We characterize the sources of nondeterminism in computers and show how to address them. In particular, we introduce a novel scheme to ensure deterministic communication on source-synchronous buses that cross clock-domain boundaries. Experiments show that CADRE on a 4-way multiprocessor server enables cycle-accurate deterministic execution of one-second intervals with modest buffering requirements (around 200MB) and minimal performance loss (around 1%). Moreover, CADRE has modest hardware requirements