EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesSystem-on-chip DesignCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyHigh-frequency Semiconductor DevicesIntegrated Circuit DesignIntegrated Circuit DevicesRadio-frequency Integrated CircuitsComplementary Metal-oxide-semiconductor DevicesIntegrated Circuit NoiseNoise In Field-effect TransistorsNoise In High-frequency Semiconductor DevicesNoise In Metal-oxide-semiconductor Field-effect TransistorsNoise Performance AnalysisSubstrate CouplingSubstrate Noise Coupling
This paper reviews the merits of incorporating deep n-well implantation in state-of-the-art CMOS technologies to address mixed-mode coupling in integrated circuits. The deep n-well architecture, coupled with novel body biasing techniques and the use of p+ guard ring, have resulted in a maximum of 35 dB reduction in substrate noise at 100 MHz. Furthermore the deep n-well implantation does not impact the dc, ac, rf and noise performance of the multi-fingered transistor, hence allowing model consistency with the standard well multi-fingered transistor. 1.
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