Enhanced bus invert encodings for low-power

Abstract

The advent of portable digital devices has made low power CMOS circuit design an increasingly important research area. Till now, most efforts in low-power CMOS design have focused on reducing the power dissipated dynamically by reducing the number of transitions inside the CMOS circuit. It has been known that a significant power reduction can be achieved by using a bus encoding to reduce the number of transitions on high capacitance I/O lines at the cost of increasing the number of transitions inside the CMOS circuit on low capacitance lines. In this paper we extend the ideas of bus invert encoding and propose two enhanced encoding schemes which further reduce the number of transitions on I/O lines. We provide a set of comparisons among the three schemes in the light of the average number of transitions, additional area overhead, encoding/decoding cost, and delay.