Two techniques for minimizing power dissipation in scan circuits during test application

Abstract

Two techniques for reducing power dissipation during test application, when scan test structure is used, are proposed. Problems required to exploit these techniques are defined. They are shown to be intractable. Heuristics required to exploit the proposed techniques are discussed. Experimental results are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>